ECE 530 Physical Design of Digital Integrated Circuits
Introduces physical design of low power and high performance digital integrated circuits including SoCs with the goal of delivering layout clean database for fabrication of ICs in foundries. Topics covered include all physical design steps such as floorplanning, placement, clock tree synthesis and routing, low power design with IEEE UPF (Unified Power Format), IP (Intellectual Property) design and integration, variation modeling for maximizing yield, implementation of testing circuits, multi-corner multi-mode performance, convergence, and manual fixing of design rules. Expected Prep:
ECE 581.